CPU - DFT Engineer

Apple

Company Type
Experience
Workhours
  • Job Number: 40350422
  • Santa Clara Valley, California, United States
  • Posted: Oct. 21, 2016
  • Weekly Hours: 40.00

Job Summary

In this highly visible role, you will be at the center of a processor design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.

Key Qualifications

  • The ideal candidate will have 5+ years of DFT experience, leading DFT efforts for large processor and/or SOC designs
  • Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
  • Experience developing DFT specifications and driving DFT architecture and methods for designs
  • Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools
  • Knowledge of industry standards DFT and design tools
  • Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
  • Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations
  • Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data

Description

As a DFT engineer owning the complete DFT solutions for a processor project, you will have responsibilities spanning all aspects of processor design:

Working with SOC DFT team to document processor DFT specifications and define the SOC-processor test interface Developing and implementing DFT architecture Implementing DFT infrastructure Working with the DV team to verify DFT implementations and implement ECOs Generating structural test vectors and analyzing and improving coverage Working with designers on STA, physical, power and logical issues Working with test engineers to bring up test vectors on silicon Managing schedules and supporting cross-functional engineering effort

Education

BSEE / MSEE is required

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Confirmed 16 hours ago. Posted 30+ days ago.

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