Design Verification Engineer


Company Type
  • Job Number: 31782468
  • Austin, Texas, United States
  • Posted: Dec. 21, 2016
  • Weekly Hours: 40.00

Job Summary

The Design Verification Engineer will be responsible for verifying internal and external IP in RTL, gate level, and power-intent environments.

Key Qualifications

  • The ideal candidate will have at least 3+ years of relevant experience including:
  • Expertise with Verilog and/or VHDL
  • Expertise with HDL simulators and waveform viewers like IES, VCS, DVE, Verdi
  • Strong knowledge of Computer Architecture; Graphics architecture is a strong plus
  • Experience with Perl, Shell scripting, Makefiles, TCL
  • Experience working under strict schedule deadlines with the ability to manage multiple priorities
  • Excellent communication skills and ability to collaborate
  • Experience with linting tools; Spyglass is a strong plus
  • Experience with code repositories; Perforce is a strong plus
  • Experience with Formal Property Checking is a plus; Jasper is a strong plus
  • Experience with verification language such as SystemVerilog/UVM/OVM is a plus


•Write, execute, and track to test plans •Simulation-based RTL verification •Create and maintain Verilog and VHDL testbenches and BFMs •Generate stimulus, implement and analyze functional coverage •Triage and debug fails •Run lint tools and analyze the results •Run and debug gate-level simulation in zero-delay and SDF environments •Power intent verification •Verify array functionality with simulation and functional equivalence tools •Integrate hierarchical designs •Create automated verification flows •Work with other engineers to ensure seamless verification flow


PHD/MSEE preferred; or BSEE plus equivalent level of experience

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Confirmed 30+ days ago. Posted 30+ days ago.

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