DDR PHY Design Engineer


Company Type
  • Job Number: 40690426
  • Santa Clara Valley, California, United States
  • Posted: Dec. 19, 2016
  • Weekly Hours: 40.00

Job Summary

In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and PD design teams, with a critical impact on delivering best in class PHY designs. You will be required to do designs of best in class PHY design

Key Qualifications

  • The ideal candidate will have 5+ years of DDR PHY Design experience on high performance, low power SOC designs
  • Knowledge about industry standards and practices in PHY Design, including RTL writing, verification tools of RTL
  • Experience in developing and implementing DDR PHY
  • Solid Understanding of all aspects of PHY construction, Integration and Physical Design
  • Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to work with design team for timing fixes
  • Knowledge of circuit design, transistor operation is a plus
  • Power user of industry standard RTL Design & Synthesis tools
  • Solid Understanding of scripting languages such as Perl/Tcl
  • Working knowledge of Extraction and STA methodology and tools
  • Good understanding of Design methodology to debug issues at PHY level


As a DDR PHY Design engineer you will be involved with all phases of PHY design of high performance DDR interface from architecture, RTL to delivery of our final GDSII.

Your responsibilities include but are not limited to:

Participate in the architecture of next generation DDR PHY. Design DDR PHY from architecture to micro-architecture. RTL implementation of the micro-architecture. Participate in clearly defining specification, testing and verification of the DDR PHY design. Work closely with CAD, PD teams to implement RTL design into GDS. Run various design verification flow at PHY level and provide guidelines to other designers. Participate in establishing CAD and design methodologies for correct by construction designs. Assist in flow development for PHY integration.


BSEE / MSEE is required

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Confirmed 30+ days ago. Posted 30+ days ago.

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