In this highly visible role, you will be at the center of a chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
As a memory sub-system verification engineer owning the verification of a certain level of memory subsystem, you will have the responsibilities as follows:
•Develop the verification infrastructure and methodology to verify the memory hierarchy on Simulation and Emulation both on unit and full chip level. •Develop checkers and C-base Xators. •Work closely with architecture and RTL designers on verifying the functionality correctness of the cache design. •Develop test plans for unit and full chip environment. •Develop stimulus in assembly, C, or vectors according to test plans. •Develop coverage monitors, collect coverage to achieve coverage closure of the design •Write assertions/properties and apply formal verification
BS, MS, or Ph.D. in Computer Engineering, Electrical Engineering, or Computer is required.