Formal Verification Engineer


Company Type
  • Job Number: 29861868
  • Orlando, Florida, United States
  • Posted: Jan. 26, 2017

Job Summary

The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification utilizing formal and property checking methods. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be leveraged to close testing coverage with high confidence..

Key Qualifications

  • The ideal candidate will have at least 4+ years of experience including:
  • Advanced knowledge of CPU or preferably GPU design architectures, VLSI circuits, and digital logic design
  • Experience in formal verification and analysis of pipelined micro-architectures, MMU’s, and cache coherency control mechanisms
  • Strong experience with formal tools, such as Jasper, IFV, etc.
  • Deep understanding of abstraction techniques and formal verification technologies
  • Knowledge and experience in reviewing and interpreting hardware specifications
  • Experience with HDL's such as Verilog/System Verilog and temporal logic assertion-based languages such as SVA
  • Hands-on experience in using EDA formal verification tools. Experience in using academic tools is a plus
  • Proficiency in programming/scripting languages with excellent debugging skills
  • Knowledge of constrained random verification methods is a plus
  • Excellent communication skills and ability to collaborate


Work with the design team to review and enhance hardware specifications

Develop verification plans in coordination with design leads and architects

Develop and drive to closure formal verification proofs across multiple design blocks

Conduct formal verification reviews and review formal proofs with design and verification teams

Manage deliverables and work with cross-functional teams to support product requirements

Create automated verification flows for block verification

Work with other block and core level engineers to ensure seamless verification flow



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Confirmed 30+ days ago. Posted 30+ days ago.

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