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Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Madison, WI, USA.

Minimum qualifications:

  • Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience
  • Experience with Logic Design

Preferred qualifications:

  • Master's degree in Electrical Engineering or Computer Science
  • Experience applying engineering best practices (e.g., code review, testing, refactoring)
  • Knowledge of machine learning
  • Solid understanding of computer architecture and memory subsystem architecture

About the Job

In this role, you will be part of a team developing cutting-edge ASICs used to accelerate machine learning computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as architecture, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of TPUs.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $105,000-$152,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Contribute to the architecture/microarchitecture of specifications.
  • Develop SystemVerilog RTL to implement logic for ASIC/SoC products.
  • Create simple test benches and debug complex logic simulations.
  • Contribute to design methodology, libraries, and code review.
  • Work closely with software teams to ensure end to end solutions.
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Confirmed 9 hours ago. Posted 30+ days ago.

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