Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Join our Central EDA PESG Static Checks team for an exciting opportunity to work on different static checks.
Who You Are
Responsibilities may be quite diverse in a technical nature and will vary significantly depending on the unique needs of the role, U.S. experience and education requirements.
As a Logic Design Methodology Engineer Graduate Intern, you would:
Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.
In this role responsibilities include although not limited to:
Note: This internship is for Spring/Summer 2024 Start
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
The candidate must be pursuing Master's degree -OR- PhD in Electrical Engineering, Computer Science, Computer Engineering or related field and have 3+ months experience in the following:
Preferred Qualifications:
NOTE: Minimum length of internship is 3 months Preferred length of internship is 6 to 9 months.
Student / Intern
Shift 1 (United States of America)
US, California, Santa Clara
US, Arizona, Phoenix, US, Massachusetts, Hudson, US, Oregon, Hillsboro
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$63,000.00-$166,000.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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