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Job Description: 

Job Description:

Design for Test Engineering Group (DTEG) is Intel's central DFT organization driving DFT architectures, methodologies, IPs, and automation across Intel. DTEG is looking for a strong leader to drive a high performance global team to provide quality, on-time, standardized and innovative DFT solutions. These activities include DFT architecture/methodology development and deployment, validation, fault grading, tools development, customers support, and more. This position reports into the GM of PESG. This person will partner with Intel design teams across different geos to provide optimized DFT solutions for highest quality IP and SOC designs. This person will manage DFT TFM vendor relations and drive innovation with industry partners. They will also drive DFT standardization, provide issue resolution, capture learnings, and rapidly apply across Intel.

Key role objectives include:

  • Establish and drive a DFT strategy to drive methodology convergence through the Intel product design life cycle.
  • Understand internal customer requirements and challenge to provide coherent DFT solutions.
  • Work closely with Intel design teams to co-optimize the tools, flows and methods.
  • Embrace new technologies like Machine Learning, AI and Generative AI.
  • Continually enhance organizational and leadership capabilities to create a diverse, growth-capable, high-performance team.
  • Established record of success as a senior-level leader within the DFT services area. Established record of success in managing at leadership level down to front line engineering.
  • Proven experience in building a high-performance team, developing leaders, driving change and culture
  • Candidate should have a very good understanding of various DFT techniques such as scan/ATPG, memory BIST, TAP architecture, fault grading, etc.
  • Experience leading and building teams through setting goals, schedule and staging plans along with tracking and enabling execution for the team.
  • Hands-on experience on silicon enabling and debug solutions.

Qualifications:

Qualification:

  • Bachelors, Masters, or Ph.D. in a related engineering field
  • 10+ years leadership experience
  • 10+ years of experience and deep knowledge of JTAG/TAP architecture, IEEE specs and design implementation for large SOCs.
  • 10+ years of experience in design & verification of DFT fabrics & test ports for post-silicon content. Knowledge of ATE testers.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, Oregon, Hillsboro

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$195,317.00-$341,559.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Confirmed 18 hours ago. Posted 16 days ago.

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