Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.
Job Description
We are looking for a hands-on Senior Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team that will deliver micro-architecture and implementation of the front-end digital design, including RTL, synthesis, IP integration, and block-level verification for high performance ASICs. The candidate must have good knowledge of communication/interface protocols such as CXL/PCIE (Gen-3 and above) or Ethernet.
Basic qualifications:
Required experience:
Preferred experience:
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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