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Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience.
  • 15 years of experience in Physical Design CAD and methodology.
  • Experience in coding using Perl, Python, TCL scripting languages.
  • Experience in project planning, execution and risk mitigation.

Preferred qualifications:

  • Master's degree in Computer Science, Electrical Engineering.
  • Experience in power optimization techniques.
  • Experience in low power methodology.

About the Job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Develop a project plan with key milestones, assign tasks, track progress and identify potential risk to develop a mitigation plan.
  • Lead, guide, motivate, mentor the team members to achieve optimal performance.
  • Develop all aspects of ASIC RTL to GDS Physical Design CAD methodology and flow for Power Performance Area (PPA) designs.
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Confirmed 36 minutes ago. Posted 30+ days ago.

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