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Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

  • Life at Intel
  • Diversity at Intel

The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge.

As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you.

As an IP Logic Design Engineer in the Network and Edge group you will:

  • Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
  • Participates in the definition of architecture and microarchitecture features of the block being designed.
  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  • Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  • Supports SoC customers to ensure high quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

The IP Logic Design Engineer should possess the following attributes in addition to the qualifications listed below.

  • Willingness to mentor team members and lead projects.
  • Should be a self-starter, able to drive tasks to closure.
  • The candidate should have strong communication, problem-solving, and analytical skills.
  • Strong analytical and problem-solving skills.

Qualifications:

What we need to see (Minimum Qualifications):

  • Bachelor's or master’s degree in electrical engineering and/or Computer Engineering with 4+ years of experience.
  • 3+ years’ experience with industry standard EDA tools and HDLs.
  • 3+ years’ experience with RTL design with Verilog and/or VHDL and timing analysis/closure.
  • 3+ years’ experience with RTL verification.
  • 3+ years’ experience with Perl, Python, and shell scripts.
  • 3+ years’ experience with logic debugging. 

How to Stand out (Preferred Qualifications):

  • Master's degree in Electrical Engineering and/or Computer Engineering with 5+ years of experience listed below.
  • 3+ years of experience with C/C++ programming
  • 3+ years of experience with IP networking protocols
  • 3+ years of experience with the operation of PCI Express Root Complex and End-Point.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Pennsylvania, Allentown

Additional Locations:

Business group:

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Confirmed 17 hours ago. Posted 27 days ago.

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