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Details:

Job Title: Engineer Digital 3

Pay Rate: $69.66 / hr.

Location: Azusa, CA

ZIP Code: 91702

Start Date: Right Away

Keywords: #Azusa #DigitalEngineeringJobs #Engineeringjobs

Benefits:

  • Medical / Health Benefits with multiple plan options, Flexible Spending Accounts, Dental and Vision / glasses / prescription contact lens and eye test options available.
  • On the job training / cross-training to develop and expand skills, creating opportunity for advancement and personal development. Tuition reimbursement available for relevant development opportunities.
  • Life Insurance, disability insurance, and voluntary life insurance for family members available. Accident and critical illness insurance optional.
  • Scheduled performance reviews create opportunities for advancement and pay increases.
  • We have many success stories from individuals who took advantage of the training, cross-training, and personal development opportunities for advancement. We also have success stories of individuals who desired a reliable, scheduled and consistent career with appropriate work-life balance, health benefits and good job security. Whichever way you define success, this work culture cares about team members and treats each individual with dignity, inclusion, respect and recognition.
  • A Referral Program compensates active employees for referring friends and former colleagues when the referral results in hiring the person. Our team has grown with referrals and internal promotions.

Job Description:

Required:

  • Bachelor's degree required
  • Minimum of 5yrs writing SystemVerilog and UVM as a primary job function
  • Experience with verification of designs written in VHDL
  • Experience with Linux command line workflows
  • Experience writing TCL to control verification tools
  • Demonstrated ability in root-cause analysis of test failures
  • Experience working closely with RTL designers to collaboratively resolve verification test failures
  • Experience with Git SCM using LFS and Submodules

Desired:

  • 10yrs writing SystemVerilog and UVM as a primary job function
  • Experience creating prediction models from functional requirements documentation using SystemVerilog or SystemC
  • Experience with DPI based simulator interaction for stimulus and prediction
  • Proficiency scripting in either Perl or Python for parsing and manipulating text files
  • Experience with Questa Sim and Visualizer
  • Experience with the UVM-Framework workflow
  • Experience writing split Class/xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)
  • Experience writing and maintaining Verification Plan Documents
  • Experience working on USG Contracts and the associated documentation/process expectations
  • Experience with common interface specifications used in spacecraft
  • Experience verifying designs targeting radiation hardened Virtex FPGAs

If you are interested in this role, please apply via the apply now link provided. Our overriding goal is to provide quality staffing solutions that help people, organizations, and communities succeed. Belcan is a team-driven Equal Opportunity Employer committed to workforce diversity. For more information, please visit our website at http://www.belcan.com

Belcan is a leading provider of qualified personnel to many of the world's most respected enterprises. We offer excellent opportunities for contract/temporary, temp-to-hire, and direct assignments in the engineering, IT, and professional fields. We are the employer of choice for thousands worldwide. Our overriding goal is to provide quality staffing solutions that help people, organizations, and communities succeed. Belcan is a team-driven Equal Opportunity Employer committed to workforce diversity. For more information, please visit our website at http://www.belcan.com.

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Confirmed 8 hours ago. Posted 6 days ago.

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