At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Description:
Deliver/implement IC project. The engineer should be able to act as a key team member with high efficiency and self driven.
Specific duties include:
- Frontend experienced designer for successful IP/subsystem/testchip tape-out.
- Strong self driven, independent problem solving, good communication and teamwork skills.
- Proficiency in design from SPEC to RTL , simulation, synthesis, STA and micro-architecture bring-up, testing.
- Proficiency in SoC and ASIC design flow and sign-off, especially front-end.
Position Requirements:
- Master degree with 5+ years as an experienced SoC front-end design engineer.
- Expertise in micro-architecture bring-up and Verilog RTL digital design in SoC and ASIC chips.
- Experienced in using STA, DFT and formal check tools
- Experienced in successful tape-out of SoC/ASIC chips
- Good knowledge and understanding on high performance / low power SOC and ASIC design, verification and power/timing
- Self-motivation with communication skills (spoken and written English and Mandarin)
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