Raytheon

FPGA Section Manager

We are looking for an experienced senior level FPGA Designer to join our team. The successful candidate will function as the Section Manager of a group of 8-20 FPGA design engineers. Tasks will include resource and manpower planning, career development of employees, performance and appraisal evaluations, developing training curricula, technical mentoring, and leadership skill development.

Other responsibilities include technical problem solving, project leadership, proposal writing, pursuing new business, managing budgets and schedules as the leader of development teams, and leading organizational initiatives. The candidate should expect to work closely with other section managers, the department manager, the program management office, senior managers, senior staff engineers, systems engineers, and other development team members. In addition to the Section Manager role this individual will continue to function as one of the lead designers within our firmware design group.

The Section Manager (SM) is a front line Leader and is a critical part of the engineering department leadership team. The SM will provide direct functional leadership, work assignments, performance evaluations and career development for their direct reports.

The priority of the Section Manager is to ensure that the Section delivers results by providing appropriate engineering resources for programs and initiatives led and/or supported by the Section.

The position requires broad based technical knowledge and the ability to review designs, analyses, and lead engineering investigations. Demonstrated experience as a hardware task lead, knowledge of Earned Value Management, and experience preparing both technical and cost proposals is required. Proposal execution (technical and resource management) in a leadership role is a critical function of the Section Manager.

The candidate will have a leadership role in support of the design activities leading major design efforts or multiple smaller design teams. The candidate must have the capability to solve design problems by thinking out-of-the-box when the situation calls for it. The individual will act independently, guided only by broad engineering instructions and objectives.

Responsibilities of this position include:

• Providing functional leadership and management of 8-20 design engineers, work assignments and resource allocation, career development and mentoring. Ensure assignments and partnering is cohesive and working well
• Responsible for execution of all FPGA work scope on all programs. Program firmware lead will be assigned for day to day execution. Section manager will ensure estimates provided at proposal response is executable, risk and opportunities are identified and provided to program manager. Section Manager is responsible for bid reconciliation at program start up ensuring that the scope and financial Baseline being provided to the program is executable within cost and schedule, any deltas from the time of proposal are identified as a risk, opportunity or removed from baseline.
• Section Manager will review program performance progress monthly by reviewing the latest revised estimates (LREs) and Quarterly EACs. Section Manager will review or provide Estimates at Completion (EACs)
• Participate in milestone design reviews. SM will align resources: Product line Subject matter experts and independent reviews to support the design review.
• Ensuring the Section is properly using the established processes within the Integrated Product Development System and for measuring and improving these processes.
• Reviewing program execution and capturing department metric collection
• Participate in Business capture activities, bid package generation, and Basis of Estimates (BoE).
• Developing relationships with Program Managers and other Section Managers to ensure steady work assignments for direct reports.
• Encouraging and fostering innovation and technology insertion into our product lines
• Perform as Hiring manager to increase talent base.
• Serve as a role model for behavior and conduct

In addition to the Managerial responsibilities listed above the Section manager’s Technical responsibilities include:

• Applying advanced technical principles and concepts to develop FPGA designs based on defined system architectures.
• Presenting, explaining, and refining architectural approaches in consultation with other product stakeholders.
• Assessing the impact of system architecture decisions on implementation, and recommending alternatives where appropriate.
• Developing Firmware Requirements Specifications for FPGA designs.
• Determining and following the course of action necessary to implement finished products based on the selected design approach.
• Leading a technical group developing FPGAs
• VHDL-based RTL and functional design, analysis and verification.
• Integrating FPGA designs into hardware and supporting system integration, test, and qualification.
• Design documentation and design maintenance.

Required Skills:

A minimum of 10 years professional engineering experience as a senior FPGA Designer with the following proven skills/experience

• Extensive experience in developing optimal FPGA architectures based on high level requirements.
• Experience in project team leadership, including technical, budget, staffing, and schedule management
• Proficiency with VHDL for configuring FPGAs
• Experience with FPGA and CPLD devices and development tools from Xilinx, Altera, and Lattice.
• Proficiency with functional verification test flow using VHDL with assertions.
• Proficiency with Modelsim and/or Questa Sim for functional verification
• Experience incorporating third party IP into FPGA designs, including PCIe and high speed Ethernet.
• Experience working independently in a complex system integration environment, verifying requirements and identifying and correcting defects.
• Possess, or able to obtain, Secret security clearance and COMSEC clearance.
• Experience as a lead (program FW lead, Hardware lead, IPT Lead or led a significant firmware development effort)
• Good organizational skills
• Passion for coaching people, mentoring and encouraging career development
• Demonstrated task ownership and accountability

Desired Skills

• Experience with satellite communications systems, including familiarity with security aspects of protected satellite communications systems
• Familiarity with security aspects of protected satellite communications systems.
• Linux scripting experience.
• Experience using DOORs tool for requirements capture and flow-down.
• Experience in cost estimation and metric collection
• CLUE
• Advanced firmware waveform generation techniques
• Familiarity with latest Xilinx and Altera chipsets
• Experience with Scrum / Agile execution and planning
• Familiarity with code coverage tools for evaluating test coverage.
• Familiarity with version control tools such as Clearcase or GitHub
• Good communication and presentation skills.
• Six Sigma/process improvement experience.
• Knowledge of SAS policies and procedures
• Required Education: Bachelor’s degree in Electrical Engineering or Computer Science.

Desired Education: Master’s Degree in Electrical Engineering or Computer Science.

This position requires either a U.S. Person or a Non-U.S. Person who is eligible to obtain any required Export Authorization.

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Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, age, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.