Come join us in the centralized Design for Test Engineering Group (DTEG) under the Silicon Engineering Group (SEG). We invite you to take an active part in our mission to define strong and robust DFT methodologies and develop state of the art design and verification tooling to drive products development and production effectiveness and decrease their Time-To-Market.
In this role you will engage in developing design automation and RTL verification tools, flows and methodologies. You will work on challenging technical problems, operate complex systems and large data sets. The solutions will involve technologies from various SW disciplines as well as RTL integration methodologies and productivity improvements in design flows.
- B.Sc. in Computer Science/Engineering, Electrical Engineering or Software Engineering.
- At least 3 years software tools/automation development experience
- Expertise in C++/Java/Python and scripting languages (e.g. Perl/Tcl) in Linux environment
- Good communication skills in Hebrew and English
- Fast learning ability and diligent problem solving capabilities
- A familiarity with DFT components, tools and methods is an advantage