As part of the physical design team, the candidate will be responsible for executing the block level place and route assignments from Netlist through GDS flow. The candidate will own the complete Physical Design including Floor Planning, Power Planning, Place and Route, CTS, Timing Closure, IR Drop Analysis, Physical Verification and Equivalence Checking.
Good understanding of timing, clock tree, routing, and DRC/LVS issues/solutions in complex ASIC designs is required. Ability to plan and work independently and co-ordinate with cross-functional teams is essential. Prior experience with 28nm or lower technology nodes is desired. An expertise in physical verification is desired. The job would require scripting in Tcl.
Candidate also needs to have good communication skills and ability to work as a team. Good knowledge of industry EDA tools used in Physical Design, including but not limited to Innovus/EDI, IC Compiler, QRC/StarXT, PrimeTime and Calibre.
Master’s/Bachelor’s degree in Electronic/Electrical engineering from reputed institute with 5 to 8 years’ of experience in Physical Design with more than 75% academic score.