Qualcomm

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

The engineer will be a key member of the Process Package Integration and bumping team, supporting technology development and new product introduction (NPI) across various silicon technology nodes, foundries, bumping lines, and assembly houses. This role focuses on advanced silicon integration and packaging technology development, including 2.5D/3DIC packaging. The candidate will work closely with foundry FBEOL teams, bump and assembly teams, and internal package design, process, quality, test, and product development teams to deliver best-in-class Far-BEOL process and packaging solutions for Qualcomm’s products.

The candidate will also work with bumping houses to bring up new bumping houses and production lines to expand capacity and ensure multi-source readiness.

Skill/Knowledge:

• Expertise in silicon BEOL process, interconnect, low-K and ELK dielectrics, passivation, RDL, bump, packaging, material, and equipment.
• Deep knowledge of flip-chip design/assembly and WLP, fan-out design and process.
• Strong technical skills in process, material and equipment characterization, failure analysis, DOE design and statistical data analysis, and FMEA.
• Strong technical skills in DOE design and statistical data analysis.
• Proven track record in package development for flip-chip, WLP, fan-out WLP and advanced packaging technologies.
• Expertise in manufacturing includes Far-BEOL structure evaluation, bump, package development, and new production line qualification.
• Hands-on experience in project leadership and OSAT management in flip-chip, fan-out, and advanced technologies.
• Experienced with interfacing with foundries, bumping houses, and assembly houses.
• Good understanding of wafer-to-wafer bonding process for heterogeneous integration, 3DIC and 2.xD foundry and packaging processes.
• Ability to design novel test structures for process-package interaction.
• Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
• Understanding of chip-top physical design flow and communication with package design teams.
• Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.

Additional Skills

• Good analytical and project management skills.
• Excellent capability of innovation and creativity.
• Highly motivated and committed to success of the individual and the team.
• Superior interpersonal communication skills. Publish technical reports.
• Able to work flexible hours. Occasional domestic/international travels needed.

Education Requirements

M.S. or Ph.D. in Materials Science, Mechanical engineering, chemical engineering or equivalent.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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