Job Details:

Job Description:

Intel's Silicon Engineering Group seeks a CPU Core Physical Design Engineer to work on the physical implementation of cutting-edge processor designs from RTL to manufacturing-ready GDS. This role requires experience in physical design methodologies and CPU-specific design challenges to deliver world-class, high-performance, low-power processors that power Intel's industry-leading products.

Key Responsibilities

Physical Design Implementation

• Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases
• Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex CPU cores
• Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs
• Optimize CPU designs to improve critical product parameters including power, frequency, and area

Verification & Signoff

• Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis
• Perform reliability verification, static and dynamic power integrity analysis, and layout verification
• Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance
• Ensure design quality and manufacturability across all verification domains

CPU-Specific Expertise & Optimization

• Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure
• Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization
• Implement design-for-test (DFT) methodologies specific to CPU architectures
• Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures

Technology Leadership & Innovation

• Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design
• Analyze design results and provide recommendations to improve current and future CPU microarchitectures
• Participate in development and improvement of physical design methodologies and flow automation
• Drive adoption of advanced design techniques and emerging technologies

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• 2+ years of experience in VLSI circuit design and synthesis
• 1+ years of experience in static timing analysis
• 1+ years of experience in low power design methodologies
• Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics)
• Experience with timing closure, power optimization, and signal integrity analysis

Preferred Qualifications

• Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• Experience with x86 CPU architecture and Intel processor designs
• Experience with Tcl, Perl, Python Programming
• Experience in CPU microarchitecture and high-performance design principles

What We Offer

• Competitive compensation and comprehensive benefits
• Opportunity to work on industry-leading CPU architectures and technologies
• Access to cutting-edge EDA tools and advanced process technologies
• Collaboration with world-class CPU architects and design engineers
• Professional development and career advancement opportunities
• Direct impact on products powering global computing infrastructure

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US: $104,890.00-197,230.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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