In this role you will be part of Intel-Mobileye ASIC team, working on next-gen SOC for autonomous driving solutions, using cutting edge processes.
We are looking for skilled RTL synthesis engineer to be technical leader in RTL handoff flows such as design synthesis using Design-Compiler, floor planning & hard macros placement, PLL and clocking considerations etc.
Candidate should also be able to run backend flow from placement to route inclusing clock tree synthesis to be able to spot potential problems early in the design phase.
You will own design exploration & synthesis of several blocks, complete with constraints definitions with the FE engineers, and provide continues feedback to drive design convergence. You will work with the backend team to ensure smooth RTL hand-off and with the DFT team to make sure design meets autonomous-driving grade coverage.
Automated Driving Group : Zero accidents. Mobility for all. Intel is collaborating with the world's leaders in automotive design and technology to turn visionary concepts for automated driving into reality. The Automated Driving Group (ADG) is architecting transportation for a better life and a safer world. We accelerate innovation and adoption of smart, connected, transformative, market leading automated driving solutions by delivering high performance SOC’s, modules, software and reference designs.