Google

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience in design and development of Security or Audio blocks.
• Experience with a scripting language like Perl or Python.
• Experience with DSI2 or MIPI C/D Phy.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Collaborate with architects and develop microarchitecture. Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test planning and coverage analysis.
• Develop RTL implementations that meet engaged power, performance and area goals.
• Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up. Create tools/scripts to automate tasks and track progress.
• Work with multi-disciplined and multi-site teams in Architecture, RTL design, verification, DFT and Partner Domains.