Looking for a candidate with 7~12 years of solid hands-on experience and leadershp in Physical Design. Should have good experience leading chip level implementation from Netlist to GDSII physical design implementation flow at block level (2M plus) as well as top level, including floorplanning, placement, signal & clock routing, static timing analysis, power analysis and Physical Verification & extraction using industry standard tools. Should also have good experience handling multi-million hier designs, along with the sign-off checks, EM/IR, XTalk and DFM. Stroing knowledge in either of the PERL/TCL/AWK/Shell scripting languages is an added advantage & is desirable. Experience Candidates who are self-driven and has worked in a global team environment with ownership of blocks or chips level PD with successful track record of taping out complex 32/28/16 nm SOCs will be preferred. Should have excellent problem solving skills, written & oral communication and teaming & inter-personal skills with experience in providing mentorship to junior engineers, reviewing designs and providing technical guidance.