Looking for a candidate with 4~8 years of hands-on experience in Physical Design. Should have good experience on Netlist to GDSII physical design implementation flow at block level (2M plus) as well as top level that includes floorplanning, placement, signal & clock routing experience using Synopsys ICC or Cadence EDI and Physical Verification using Mentor Caliber/Hercules for DRC/LVS. Candidates with experience on Static Timing Analysis, Power Analysis will be preferred. Candidate should have handled multi-million hier designs, along with the sign-off checks, EM/IR, XTalk and DFM. Candidates who are self-driven and has worked in a global team environment with ownership of blocks or chips level PD with successful track record of taping out complex 32/28/16 nm SOCs are desirable.
Preferred Qualifications: (Please list any skills or attributes you prefer that are not experienced or physical.)