You will work with an elete team of physical design implementation engineers and have personal design responsibility, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.
You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design.
Your responsibility includes participating in or leading next generation physical design, methodology and flow development.
You will work closely with RTL design team to ensure successful tapeouts.
This is definitely not just another physical design job , This is Cadence IPG , the fastest growing business unit in Cadence. This is where the best IP in the industry is created for now and the future. In 3 short years ,we have become the #4 provider of IP worldwide.
BS/MS in EE/CS with 12+ years of hands-on experience in physical design and verification.
Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM.
Successful track records of taping out complex, 65/40/28/10 nm SOCs.
Power user of Cadence implementation tools, such as, RC, Conformal, EDI, ETS, ET, EPS, RC.
Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills.