At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Software Engineer will be part of a team responsible for developing Cadence’s software to target functional verification of RTL designs using formal techniques. More specifically, they will work with this software’s HDL compiler, which creates an optimal formal synthesis of the designs.
- Must have:
- BS degree in Electrical Engineering/Computer Science or related field;
- Excellent C++, STL and data structures skills are required;
- Excellent verbal and written communication skills;
- Excellent problem-solving and debugging skills;
- Very good spoken and written English;
- Nice to have:
- Awareness of ASIC design flow is a plus;
- Experience with verification projects is a plus;
- Experience with EDA tools from any vendors is a plus;
- Knowledge of C++11 is a plus;
- Exposure to Cadence tools;
- Knowledge of Tcl;
- Knowledge of IP-XACT.
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