ASIC Digital Design Engr, II
PORTUGAL - Porto
PORTUGAL - Portugal
Job Description and Requirements
As a member of the Synopsys mixed signal IP RTL team you will be part of a global team implementing digital and / or mixed-signal logic blocks.
- Position responsibilities
Define, implement and support verification of semiconductor integrated digital and mixed signal circuits.
- Participate in architecture design exploration, logic design and verification. Elaborate design and verification specifications.
- Generate or contribute to high quality documentation targeting different audiences: customer consumable and to support design implementation and verification.
- Adhere to implemented development flows for RTL design, functional simulation, timing and power analysis, gathering data and achieving quality targets.
- Execute behavioral modeling.
- Participate in evaluation and troubleshooting of digital and mixed signal circuits.
- Degree in Engineering
- Knowledge of HDL languages (Verilog / SystemVerilog) and IC design flows
- Knowledge of DDR or other I/O and Memory interface and protocols is a plus
- Solid analysis and problem-solving skills
- Excellent communication and organizational skills
- Strong motivation for learning and exploring new technologies
- Willingness to be part of a geographically spread team working on cutting-edge technology
- Availability to travel occasionally