Senior ASIC Design Engineer

SpaceX

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SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. ASIC DESIGN ENGINEER 

This is a senior digital ASIC design role in the development of broadband satellite modem hardware solutions. This position includes significant responsibilities in one or more of the following areas: requirements and specifications, micro-architectural design and definition, digital design (RTL) and verification, synthesis, static timing analysis, and power estimation and optimization. 

Project deliverables may include specification documents, System Verilog RTL code, simulation models, test benches, gate-level netlists, and timing constraints. As a senior digital ASIC designer, you will be responsible for all aspects of digital ASIC design focusing on RTL design, verification, logic synthesis, and timing analysis. You will design both or either data path processing and/or control systems for advanced mixed analog/digital integrated circuits in System Verilog.

RESPONSIBILITIES: 

  • RTL design of digital circuits using hardware description languages such as Verilog and System Verilog.
  • Estimate and schedule your work so that progress can be managed by our in-house program management group.
  • Document high level description of designs and requirements for signal processing subsystems.
  • Write functional test cases to verify and debug digital designs.
  • Write scripts using languages such as TCL and PERL to achieve higher performance and improve productivity through automation.

BASIC QUALIFICATIONS: 

  • Bachelor's degree in electrical engineering, computer science or computer engineering.
  • 7+ years of work experience and experience with at least 3 ASICs in high volume production.
  • 5+ years of experience with System Verilog.
  • Previous experience with scripting languages like Perl, Python, TCL, Make or Shell.

PREFERRED SKILLS AND EXPERIENCE: 

  • Experience with either Cadence NC system Verilog tools, Mentor Questa tools, or Synopsys vcs simulators.
  • Experience in developing automated, self-checking test benches.
  • Experience in timing constraints and closure on high speed, low power designs.
  • Familiar with ASIC design methodology/flows/checks for digital designs.
  • Problem-solving skills with appropriate attention to detail.
  • Experience/knowledge in the architecture/RTL design of signal processing wireless protocols including 802.11a/b/g/n/ac or hands-on experience in any of one of LTE/WiMAX/4G/Gigabit DSP preferable.
  • Experience in the design and implementation of high speed forward error correction (FEC) codecs, such as Turbo Codes, LDPC, convolutional, and Reed-Solomon codecs.

ADDITIONAL REQUIREMENTS: 

  • Must be able to work extended hours and weekends as needed.

ITAR REQUIREMENTS:

  • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. 

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.

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Confirmed 4 hours ago. Posted 30+ days ago.

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